Nordic nRF24LU1
Single Chip 2.4GHz Transceiver with USB Microcontroller and Flash Memory

Flash programming through SPI:
P0  SCK  10
P1  MOSI 11
P2  MISO 13
P3  CSN  14
    PROG  7 to logic1 (Vcc)
    RESET 8 to logic1 (Vcc)
GND      6,12,17,18,26,30
VCC      3,9,19,24,27
XC1,XC2 - XTAL

FSR - Flash Status Register:
7 DBG RW  	1: Debug enabled, 0: Debug disabled, can be set by MCU
6 STP R 	1: Start from protected program memory
5 WEN RW 	Write enable. 1: enable
4 RDYN R 	Flash interface ready. 0: ready
3 INFEN RW 	Infopage enable. 1: enable
2 RDISMB R 	SPI read-back disable of main block. 1: read back disable
1 RDISIP R 	SPI read-back disable of infopage. 1: read back disable
0 - Reserved, read as 0.

A readback of the flash content is only possible if read disable
bits (RDISMB and RDISIP) in the FSR register are not set.

A mechanism to prevent readback over the SPI bus is implemented. Two bytes of the infopage are
reserved for this. The infopage and MainBlock each have their own readback disable signal, RDISIP and
RDISMB respectively. The signal values are available in the FSR register in bits 2:1. The infopage content is
checked whenever the chip is started or restarted. If byte 0x22 of infopage==0xFF, RDISIP=0, otherwise
RDISIP=1. If byte 0x23 of infopage==0xFF, RDISMB=0, otherwise RDISMB=1.
The infopage bytes may be written once, (by using command SPI commands RDISIP or RDISMB) which
enables the readback disable function. Until the flash memory is erased the readback cannot be enabled
again. RDISMB=1 inhibits page erase and write to flash (both MainBlock and infopage), but erase all is
always allowed, it is also the only way to clear RDISMB.


Erase Flash before write.